1. Field of the Invention
The present invention relates to a multiport register file memory army. More particularly, the present invention relates to multiport register file memory array used in a floating point processing unit of a deep submicron device.
2. The Prior Art
Memory circuitry is designed to store data bits of information at specifically addressed locations in the memory. Each address location stores the data bits in memory cells wherein each memory cell stores one data bit. The data bits are usually input or output to or from the memory cells at each addressable location in groups. These groups are called data words, and a data word is usually specified as having a width of N bits. It is conventional to denote the bit positions at a memory address as AO through AN. In a memory array, the same bit position of every address location is connected by a common bit line. In other words, the first bit position, AO, at an address location is connected to the first bit position, AO, at every other address location by a common bit line. Likewise each of the A1 bit positions are connected, as are each of the same bit positions at each address.
To access a specific address in the memory, the address is presented to decoding circuitry, i.e. an address port, and the output from the address port transmits an address select signal to a word line at the desired location in the memory array. When the address select signal is on the word line associated with a memory location data is transferred in or out of each of the individual memory cells at the specified address. The data of each memory cell is transferred on its associated bit line.
Some memory arrays, termed a multiport array, have more than one address port. Consequently, during a single read/write cycle, more than one address may be decoded and data transfer made for the decoded addresses. It is conventional that for every address port, each memory cell will have an associated bit line. In other words, if there are ten ports, then each memory cell will have ten common bit lines associated with it.
In a multiport memory array, such as the one disclosed in the reference "A 320-MFLOPS CMOS Floating-Point Processing Unit for Superscalar Processors", I. Nobohiro et al., IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, Mar. 1993, there are several common bit lines for each memory cell in the array. The multiport memory array disclosed in Nobohiro et al. has common bit lines which are split into two groups. A first group of four write bit lines for providing input to each memory cell in the array, and a second group of six read bit lines for providing output information from each memory cell in the array. The memory array shown in Nobiro et al. is a register file. It is an array of thirty-two registers, each register having its own address and each containing sixty-four bits of information stored in two data words, each thirty-two bits in length. The register file is used in a floating point processing unit integrated with a RISC core processor.
As shown in Nobohiro et al., and as is conventional, associated with each address or register in the register file there are word lines. There is a separate word line at each address for controlling each of the separate read and write bit lines. Each of the separate word lines is connected to an address port. For example, when there are N ports to the memory array, there will be N word lines for each address, and N bit lines for every bit position at any address. Accordingly, the size of the multiport memory array varies as a square of the number of ports to the array. This is the case, since, for every memory cell in the array, the number of bit lines is equal to the number of word lines, and the number of word lines for every address is the same as the number of ports to the memory array.
In the operation of a conventional multiport array, as an address is presented to one of the read or write ports, it is decoded and an address signal is transmitted to the decoded address location. The address signal is transmitted on the word line associated with the address port the address passed through. The address signal on the word line will cause the contents of each of the memory cells at the selected address to either be written to or read from. The data transfer for each memory cell takes place on the read or write bit lines, each of which is associated with a separate word line. During a single read/write cycle, a multiple number of reads up to the number of read ports may be read from the same address or different addresses and a multiple number of writes up to the number of write ports into different addresses may be made.
Since more than one read may be made from the same memory address during the same read/write cycle, the maximum amount of current to the memory cell is determined by the number of read ports. To protect the memory cell, additional buffer transistors are used in each cell for each read port. Because of the additional buffer transistors, a bit line must be either a read bit line or a write bit line, but it cannot be used as both, or in other words, as a common read/write bit line. With the use of separate bit lines for the read and write operations, separate word lines for the read and write operations are also employed.
As pointed out above, the size of the register file memory array varies according to the square of the number of ports, wherein the number of ports to the memory array is equal to both the number of word lines and bit lines. In deep submicron devices, the amount of delay introduced into a circuit due to the interconnect between circuit elements is a significant consideration. It is, in fact, often a more important consideration than gate delay. One way to reduce the interconnect delay is to reduce the length of bit lines and word lines. This can be accomplished by reducing the size of the register file memory array.
It is therefore an object of the present invention to reduce the area of the multiport register file memory array to minimize interconnect delay.
It is another object of the present invention to minimize the interconnect delay in the multiport register file memory array to increase the frequency of the memory access cycles to the multiport register file memory array.
It is another object of the present invention to reduce the area of the multiport register file memory array having N ports by reducing the number of word lines for each memory cell from N to between log.sub.2 N and N/2+1.
It is another object of the present invention that for a multiport register file memory array of N ports to have N bit lines and between log.sub.2 N and N/2+1 word lines for each memory cell.